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Silicon Labs /EFR32FG23B010F512IM48 /I2C0_S /STATE

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Interpret as STATE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BUSY)BUSY 0 (MASTER)MASTER 0 (TRANSMITTER)TRANSMITTER 0 (NACKED)NACKED 0 (BUSHOLD)BUSHOLD 0 (IDLE)STATE

STATE=IDLE

Description

No Description

Fields

BUSY

Bus Busy
MASTER

Leader
TRANSMITTER

Transmitter
NACKED

Nack Received
BUSHOLD

Bus Held
STATE

Transmission State

0 (IDLE): No transmission is being performed.

1 (WAIT): Waiting for idle. Will send a start condition as soon as the bus is idle.

2 (START): Start transmit phase

3 (ADDR): Address transmit or receive phase

4 (ADDRACK): Address ack/nack transmit or receive phase

5 (DATA): Data transmit or receive phase

6 (DATAACK): Data ack/nack transmit or receive phase

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data